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| HD6417705 Datasheet, PDF (690/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series | |||
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Ta1
Ta2
Ta3
T1
Tw
Tw
T2
CKIO
tAD1
tAD1
A25 to A0
CSn
tCSD1
tCSD1
RD/WR
AH
tRWD1
tAHD
tAHD
tRWD1
RD
Read
D15 to D0
WE0/1
Write
D15 to D0
tBSD
BS
tRSD
tMAD
tMAD
tBSD
tMAH
Address
tWED
tWDD1
tMAH
Address
tRSD
tRDH1
tRDS1
Data
tWED
Data
tWDH1
WAIT
DACKn*
tDACD
tWTH
tWTS
tWTH
tWTS
tDACD
Note: * DACKn is a waveform when active-low is specified.
Figure 25.20 Address/Data Multiplex I/O Bus Cycle
(Three Address Cycles, One Software Wait, One External Wait)
Rev. 2.00, 09/03, page 644 of 690
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