HD6417705 Datasheet, PDF (275/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8.10 Power-On Sequence
In order to use synchronous DRAM, mode setting must first be performed after powering on. To
perform synchronous DRAM initialization correctly, the bus state controller registers must first be
set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode
register setting, the address signal value at that time is latched by a combination of the CSn, RAS,
CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X
to be written to the synchronous DRAM mode register by performing a write to address
H'A4FD4000 + X for area 2 synchronous DRAM, and to address H'A4FD5000 + X for area 3
synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a
word-size access. To set burst read/single write, CAS latency 2 to 3, wrap type = sequential, and
burst length 1 supported by the LSI, arbitrary data is written in a word-size access to the addresses
shown in table 7.17. In this time 0 is output at the external address pins of A12 or later.
Table 7.17 Access Address in SDRAM Mode Register Write
(1) Setting for Area 2 (SDMR2)
Burst read/single write (burst length 1):
Data Bus Width
16 bits
32 bits
CAS Latency
2
3
2
3
Access Address
H'A4FD4440
H'A4FD4460
H'A4FD4880
H'A4FD48C0
External Address Pin
H'0000440
H'0000460
H'0000880
H'00008C0
Burst read/burst write (burst length 1):
Data Bus Width
16 bits
32 bits
CAS Latency
2
3
2
3
Access Address
H'A4FD4040
H'A4FD4060
H'A4FD4080
H'A4FD40C0
External Address Pin
H'0000040
H'0000060
H'0000080
H'00000C0
Rev. 2.00, 09/03, page 229 of 690