HD6417705 Datasheet, PDF (492/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.3.10 EP1 Data Register (EPDR1)
EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When one packet of data is received
successfully, EP1FULL in interrupt flag register 0 is set, and the number of receive bytes is
indicated in the EP1 receive data size register. After the data has been read, the buffer that was
read is enabled to receive data again by writing 1 to the EP1RDFN bit in the trigger register. The
receive data in this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by
means of EP1CLR in the FCLR register.
Bit
7 to 0
Bit Name
D7 to D0
Initial Value R/W
Undefined
R
Description
Data register for endpoint 1 transfer
18.3.11 EP2 Data Register (EPDR2)
EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO
buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the
dual-FIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by
DMA. This FIFO buffer can be initialized by means of EP2CLR in the FCLR register.
Bit
7 to 0
Bit Name
D7 to D0
Initial Value R/W
Undefined
W
Description
Data register for endpoint 2 transfer
18.3.12 EP3 Data Register (EPDR3)
EPDR3 is an 8-byte transmit FIFO buffer for endpoint 3. EPDR3 holds one packet of transmit data
for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and
setting EP3PKTE in the trigger register. When an ACK handshake is returned from the host after
one packet of data has been transmitted successfully, EP3TS in interrupt flag register 0 is set. This
FIFO buffer can be initialized by means of EP3CLR in the FCLR register.
Bit
7 to 0
Bit Name
D7 to D0
Initial Value R/W
Undefined
R
Description
Data register for endpoint 3 transfer
Rev. 2.00, 09/03, page 446 of 690