HD6417705 Datasheet, PDF (163/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Exception Current
Type
Instruction Exception Event
Exception Process Vector Vector
Priority^*1 Order
at BL=1 Code Offset
General Re-executed TLB invalid ^*4 (data access) 2
exception
events
TLB protection violation ^*4 2
(data access)
Initial page write ^*4
2
(data access)
3-2
Reset H'040/ H'00000100
H'060
3-3
Reset H'0A0/ H'00000100
H'0C0
3-4
Reset H'080 H'00000100
Completed Unconditional trap (TRAPA 2
4
Reset H'160 H'00000100
instruction)
User breakpoint (After
2
5
Ignored H'1E0 H'00000100
instruction execution, address)
General Completed User breakpoint
2
interrupt
(Data break, I-BUS break)
requests
DMA address error
2
Interrupt Completed Interrupt requests
3
requests
5
Ignored H'1E0 H'00000100
6
Retained H'5C0 H'00000100
—^*2
Retained —^*3 H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest.
A reset has the highest priority. An interrupt is accepted only when general exceptions
are not requested.
2. For details on priorities in multiple interrupt sources, refer to section 6, Interrupt
Controller (INTC).
3. If an interrupt is accepted, the exception event register (EXPEVT) is not changed. The
interrupt source code is specified in interrupt source register 2 (EXPEVT2). For details,
refer to section 6, Interrupt Controller (INTC).
4. These exception codes are valid when the MMU is used.
Rev. 2.00, 09/03, page 117 of 690