HD6417705 Datasheet, PDF (481/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

17.4.3 Receiving
Received 3/16 IR frame bit-width pulses are demodulated and converted to a UART frame, as
shown in figure 17.2.
Demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse
output.
UART frame
Start bit
UART frame
Data
01 0 1 00 1 1 0 1
Stop bit
IR frame
Start bit
Transmit
01
Receive
IR frame
Data
01
0 01 1
01
Stop bit
Bit cycle
3/16-bit cycle
pulse width
Figure 17.2 Transmit/Receive Operation
17.4.4 Data Format Specification
The data format of UART frames used for IrDA communication must be specified by the SCIF0
registers. The UART frame has eight data bits, no parity bit, and one stop bit.
IrDA communication is performed in asynchronous mode, and this mode must also be specified
by the SCIF0 registers. The sampling rate must be set to 1/16.
The internal clock must be selected for the SCIF0 operation clock and the SCK0 pin must be
specified for the synchronizing clock output pin.
The IrDA communication rate is the same as the SCIF0 bit rate, which is specified by the SCIF0
registers.
For details on SCIF0 registers, refer to section 16, Serial Communication Interface with FIFO
(SCIF).
Rev. 2.00, 09/03, page 435 of 690