HD6417705 Datasheet, PDF (715/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

25.3.8 TMU Signal Timing
Table 25.10 TMU Signal Timing
(Conditions: VCCQ = VCC-RTC = VCC-USB = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to
1.6 V, AVCC = 3.0 to 3.6 V, VSSQ = VSS = VSS-RTC = VSS-USB = VSS-PLL1 = VSS-PLL2 =
AVSS = 0 V, Ta = –20 to 75°C)
Module Item
Symbol Min
Max Unit Figure
TMU
Timer input B:P clock ratio = 1:1 tTCLKS
15
—
setup time _{B:P clock ratio = 2:1}
tcyc+15
—
B:P clock ratio = 4:1
3 × tcyc+15 —
Timer clock input setup time
tTCKS
15
—
Timer clock Edge specification tTCKWH/L 2.0
—
pulse width
ns
25.45
tpcyc^*
25.46
Both edge
tTCKWH/L 3.0
—
specification
Note: * tpcyc indicates a peripheral clock (Pφ) cycle.
CKIO
TCLK
(input)
t_TCLKS
Figure 25.45 TCLK Input Timing
CKIO
TCLK
(input)
t_TCKS
t_TCKS
t_TCKWL
t_TCKWH
Figure 25.46 TCLK Clock Input Timing
Rev. 2.00, 09/03, page 669 of 690