HD6417705 Datasheet, PDF (19/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Contents
Section 1 Overview ....................................................................................... 1
1.1 SH7705 Features.......................................................................................................... 1
1.2 Block Diagram............................................................................................................. 6
1.3 Pin Assignment............................................................................................................ 7
1.4 Pin Functions............................................................................................................... 17
Section 2 CPU ............................................................................................... 25
2.1 Processing States and Processing Modes....................................................................... 25
2.1.1 Processing States ............................................................................................. 25
2.1.2 Processing Modes............................................................................................ 26
2.2 Memory Map ............................................................................................................... 27
2.2.1 Logical Address Space..................................................................................... 27
2.2.2 External Memory Space................................................................................... 28
2.3 Register Descriptions ................................................................................................... 29
2.3.1 General Registers ............................................................................................ 32
2.3.2 System Registers ............................................................................................. 33
2.3.3 Program Counter ............................................................................................. 34
2.3.4 Control Registers............................................................................................. 35
2.4 Data Formats ............................................................................................................... 37
2.4.1 Register Data Format....................................................................................... 37
2.4.2 Memory Data Formats..................................................................................... 38
2.5 Features of CPU Core Instructions ............................................................................... 40
2.5.1 Instruction Execution Method .......................................................................... 40
2.5.2 CPU Instruction Addressing Modes ................................................................. 42
2.5.3 CPU Instruction Formats ................................................................................. 45
2.6 Instruction Set.............................................................................................................. 48
2.6.1 CPU Instruction Set Based on Functions .......................................................... 48
2.6.2 Operation Code Map ....................................................................................... 62
Section 3 Memory Management Unit (MMU) ............................................... 65
3.1 Role of MMU .............................................................................................................. 65
3.1.1 MMU of This LSI............................................................................................ 67
3.2 Register Descriptions ................................................................................................... 72
3.2.1 Page Table Entry Register High (PTEH) .......................................................... 72
3.2.2 Page Table Entry Register Low (PTEL) ........................................................... 73
3.2.3 Translation Table Base Register (TTB) ............................................................ 73
3.2.4 MMU Control Register (MMUCR) .................................................................. 73
3.3 TLB Functions............................................................................................................. 75
3.3.1 Configuration of the TLB ................................................................................ 75
Rev. 2.00, 09/03, page xix of xlvi