HD6417705 Datasheet, PDF (220/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
6, 5 
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
TRWL1 0
R/W Number of Cycles from WRITA/WRIT Command to Auto-
3
TRWL0 0
R/W ^{precharge/PRE Command}
Specifies the number of cycles from issuing WRITA/WRIT
command to the start of auto-precharge or to issuing PRE
command. The setting for areas 2 and 3 is common.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: Setting prohibited
2

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
1
TRC1 0
R/W Number of Cycles from REF Command/Self-refresh Release
0
TRC0 0
R/W ^{to ACTV Command}
Specify the number of cycles from issuing the REF command
or releasing self-refresh to issuing the ACTV command. The
setting for areas 2 and 3 is common.
00: 3 cycles
01: 4 cycles
10: 6 cycles
11: 9 cycles
Note: * Specify area 3 as SDRAM when only one area is connected with SDRAM. In this case,
specify area 2 as normal space.
7.4.4 SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
The bits other than RFSH and RMODE should be written in the initialization after a power-on
reset and should not be modified after the initialization. When modifying these bits RFSH and
RMODE, do not change the values of other bits and write the previous values. Do not access area
2 or 3 until the SDCR register setting is complete when using synchronous DRAM.
Rev. 2.00, 09/03, page 174 of 690