HD6417705 Datasheet, PDF (293/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Descriptions
1
TE
0
R/(W)^* Transfer End Flag
Indicates that the DMA transfer ends. The TE bit is set to 1
when data transfer ends when DMATCR becomes to 0.
The TE bit is not set to 1 in the following cases.
• DMA transfer ends due to an NMI interrupt or DMA address
error before DMATCR becomes to 0.
• DMA transfer is ended by clearing the DE bit and the DME
bit in the DMA operation register (DMAOR).
This bit can only be cleared by writing 0 after reading 1. Even if
the DE bit is set to 1 while this bit is set to 1, transfer is not
enabled.
0: During the DMA transfer or DMA transfer has been aborted
[Clearing conditions]
• Writing 0 after reading TE = 1
• Power-on reset
• Manual reset
1: Data transfer ends by the specified count (DMATCR = 0)
0
DE
0
R/W DMA Enable
Enables or disables the DMA transfer. In auto request mode,
DMA transfer starts by setting the DE bit and DME bit in
DMAOR to 1. In this time, all of the bits TE, NMIF in DMAOR,
and AE must be 0. In an external request or peripheral module
request, DMA transfer starts if DMA transfer request is
generated by the devices or peripheral modules after setting
the bits DE and DME to 1. In this case, however, all of the bits
TE, NMIF, and AE must be 0 an in the case of auto request
mode. Clearing the DE bit to 0 can terminate the DMA transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Note: * Only 0 can be written for clearing the flags.
Rev. 2.00, 09/03, page 247 of 690