HD6417705 Datasheet, PDF (494/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.3.15 Trigger Register (TRG)
TRG generates one-shot triggers to control the transfer sequence for each endpoint.
Bit Bit Name Initial Value R/W Description
7

Undefined 
Reserved
The write value should always be 0.
6
EP3PKTE Undefined W
EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
5
EP1RDFN Undefined W
EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint
1 receive FIFO buffer has a dual-buffer
configuration. Writing 1 to this bit initializes the FIFO
that was read, enabling the next packet to be
received.
4
EP2PKTE Undefined W
EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
3

Undefined 
Reserved
The write value should always be 0.
2
EP0sRDFN Undefined W
EP0s Read Complete
Write 1 to this bit after data for the EP0s command
FIFO has been read. Writing 1 to this bit enables
transfer of data in the following data stage. A NACK
handshake is returned in response to transfer
requests from the host in the data stage until 1 is
written to this bit.
1
EP0oRDFN Undefined W
EP0o Read Complete
Writing 1 to this bit after one packet of data has
been read from the endpoint 0 transmit FIFO buffer
initializes the FIFO buffer, enabling the next packet
to be received.
0
EP0iPKTE Undefined W
EP0i Packet Enable
After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
Rev. 2.00, 09/03, page 448 of 690