HD6417705 Datasheet, PDF (512/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

(1) Transition from normal operation to stall
(1-1)
USB
Internal status bit
0
(1-2)
Transaction request
Reference
Internal status bit
0
EPSTL
0→1
EPSTL
1
1. 1 written to EPSTL
by application
1. IN/OUT token
received from host
2. EPSTL referenced
(1-3)
STALL handshake
Stall
Internal status bit
0→1
EPSTL
1
To (2-1) or (3-1)
(2) When Clear Feature is sent after EPSTL is cleared
(2-1)
Transaction request
Internal status bit
1
EPSTL
1→0
(2-2)
STALL handshake
Internal status bit
1
EPSTL
0
1. 1 set in EPSTL
2. Internal status bit
set to 1
3. Transmission of
STALL handshake
1. EPSTL cleared to 0
by application
2. IN/OUT token
received from host
3. Internal status bit
already set to 1
4. EPSTL not
referenced
5. Internal status bit
not changed
1. Transmission of
STALL handshake
(2-3)
Clear Feature command
Internal status bit
1→0
EPSTL
0
1. Internal status bit
cleared to 0
Normal status restored
(3) When Clear Feature is sent before EPSTL is cleared to 0
(3-1)
Clear Feature command
Internal status bit
1→0
EPSTL
1
1. Internal status bit
cleared to 0
2. EPSTL not changed
To (1-2)
Figure 18.13 Forcible Stall by Application
Rev. 2.00, 09/03, page 466 of 690