HD6417705 Datasheet, PDF (289/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

8.3.3 DMA Transfer Count Registers (DMATCR)
DMATCR are 32-bit readable/writable registers that specify the DMA transfer count. The number
of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and
16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers
indicate the remaining transfer count.
The upper 8 bits of DMATCR are always read as 0. The write value should always be 0. To
transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The initial value is undefined.
The DMATCR retains the current value in software standby or module standby mode.
8.3.4 DMA Channel Control Registers (CHCR)
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Bit
Bit Name
31 to 24 
23
DO
22
TL
21 to 18 
Initial
Value R/W Descriptions
0
R
Reserved
These bits are always read as 0. The write value should always
be 0.
0
R/W DMA Overrun
Selects whether DREQ is detected by overrun 0 or by overrun
1. This bit is valid only in CHCR_0 and CHCR_1. This bit is
always read as 0 in CHCR_2 and CHCR_3. The write value
should always be 0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
0
R/W Transfer End Level
Selects whether the TEND signal output is high active or low
active. This bit is valid only in CHCR_0. There are no TEND
pins in CHCR_1 to CHCR_3. Therefore this setting is invalid.
This bit is always read as 0. The write value should always be
0.
0: Low-active output of TEND
1: High-active output of TEND
0
R
Reserved
These bits are always read as 0. The write value should always
be 0.
Rev. 2.00, 09/03, page 243 of 690