HD6417705 Datasheet, PDF (52/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

1.2 Block Diagram
Figure 1.1 shows an internal block diagram of the SH7705.
CCN
CACHE
MMU
SH3
CPU
UBC
AUD
TMU
TPU
RTC
CMT
TLB
INTC
CPG/WDT
BSC
DMAC
SCIF0/IrDA
SCIF2
USB
ADC
External bus
interface
Legend:
CACHE: Cache memory
CCN:
Cache memory controller
MMU:
Memory management unit
TLB:
Translation look-aside buffer
INTC:
Interrupt controller
CPG/WDT: Clock pulse generator/watchdog timer
CPU:
Central processing unit
UBC:
User break controller
AUD:
Advanced user debugger
BSC:
Bus state controller
DMAC: Direct memory access controller
I/O port
UDI
(PFC)
TMU:
TPU:
RTC:
CMT:
SCIF:
IrDA:
USB:
ADC:
UDI:
PFC:
Timer unit
16-bit timer pulse unit
Realtime clock
Compare match timer
Serial communication interface with FIFO
Infrared data association module
Universal serial bus
A/D converter
User debugging interface
Pin function controller
Figure 1.1 Block Diagram of SH7705
Rev. 2.00, 09/03, page 6 of 690