HD6417705 Datasheet, PDF (433/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit
Name Value R/W Description
5
TE
0
R/W Transmit Enable
Enables or disables the start of serial transmission by
the SCIF.
0: Transmission disabled
1: Transmission enabled^*
Note: * The serial mode register (SCSMR) and FIFO
control register (SCFCR) settings must be made,
the transmit format decided, and the transmit
FIFO reset, before the TE bit is set to 1.
4
RE
0
R/W Receive Enable
3, 2

0
Enables or disables the start of serial reception by the
SCIF.
0: Reception disabled^*1
1: Reception enabled^*2
Notes: 1. Clearing the RE bit to 0 does not affect the
DR, ER, BRK, RDF, FER, PER, and ORER
flags, which retain their state.
2. The serial mode register (SCSMR) and FIFO
control register (SCFCR) settings must be
made, the receive format decided, and the
receive FIFO reset, before the RE bit is set to
1.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 387 of 690