HD6417705 Datasheet, PDF (203/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
5
DMAIWA 0
R/W Method of inserting wait states between access cycles when
DMA single address transfer is performed.
Specifies the method of inserting the idle cycles specified by
the DMAIW1 and DMAIW0 bits. Clearing this bit will make this
LSI insert the idle cycles when another device, which includes
this LSI, drives the data bus after an external device with
DACK drove it. Setting this bit will make this LSI insert the idle
cycles even when the continuous accesses to an external
device with DACK are performed.
4

1
R
Reserved
This bit is always read as 1. The write value should always be
1.
3
ENDIAN 0/1^* R
Endian Flag
Samples the external pin for specifying endian on power-on
reset (MD5). All address spaces are defined by this bit. This is
a read-only bit.
0: The external pin for specifying endian (MD5) was low level
on power-on reset. This LSI is being operated as big
endian.
1: The external pin for specifying endian (MD5) was high level
on power-on reset. This LSI is being operated as little
endian.
2

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
1
HIZMEM 0
R/W High-Z Memory Control
Specifies the pin state in software standby mode for A25 to
A0, BS, CS, RD/WR, WE, and RD.
0: High impedance in software standby mode.
1: Driven in software standby mode
0
HIZCNT 0
R/W High-Z Control
Specifies the state in software standby mode and bus
released for RASU, RASL, CASU, and CASL.
0: High impedance in software standby mode and bus
released for RASU, RASL, CASU, and CASL.
1: Driven in standby mode and bus released for RASU,
RASL, CASU, and CASL.
Note: * The external pin for specifying endian (MD5) is sampled on power-on reset.
When big endian is specified, this bit is read as 0 and when little endian is specified,
this bit is read as 1.
Rev. 2.00, 09/03, page 157 of 690