HD6417705 Datasheet, PDF (497/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit Bit Name Initial Value R/W Description
1
EP2DMAE 0
R/W Endpoint 2 DMA Transfer Enable
When this bit is set, DMA transfer is enabled from
memory to the endpoint 2 transmit FIFO buffer. If there is
at least one byte of space in the FIFO buffer, a transfer
request is asserted for the DMAC. In DMA transfer, when
64 bytes are written to the FIFO buffer the EP2 packet
enable bit is set automatically, allowing 64 bytes of data
to be transferred, and if there is still space in the other of
the two FIFOs, a transfer request is asserted for the
DMAC again. However, if the size of the data packet to
be transmitted is less than 64 bytes, the EP2 packet
enable bit is not set automatically, and so should be set
by the CPU with a DMA transfer end interrupt.
As EP2-related interrupt requests to the CPU are not
automatically masked, interrupt requests should be
masked as necessary in the interrupt enable register.
• Operating procedure
1. Write of 1 to the EP2 DMAE bit in DMAR
2. Transfer count setting in the DMAC
3. DMAC activation
4. DMA transfer
5. DMA transfer end interrupt generated
Refer to section 18.7.3, DMA Transfer for Endpoint 2.
Rev. 2.00, 09/03, page 451 of 690