HD6417705 Datasheet, PDF (453/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

b. Serial Data Transmission
Figure 16.3 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission
Read TDFE bit in SCSSR
[1]
No
TDFE = 1?
Yes
Write (64) − transmit trigger
set number) bytes of transmit
data to SCFTDR, read 1 from
TDFE bit in SCSSR, then clear to 0
All data transmitted?
Yes
No [2]
Read TEND bit in SCSSR
TEND = 1?
Yes
Break output?
Yes
Set SCPDR and SCPCR
No
No [3]
[1] SCIF status check and transmit data write:
Read the serial status register (SCSSR) and
check that the TDFE flag is set to 1, then write
transmit data to SCFTDR, read 1 from the TDFE
flag, then clear the flag to 0.
The number of data bytes that can be written is
64 − (transmit trigger set number).
[2] Serial transmission continuation procedure:
To continue serial transmission, read 1 from the
TDFE flag to confirm that writing is possible, then
write data to SCFTDR, and then clear the TDFE
bit to 0.
[3] Break output at the end of serial transmission:
To output a break in serial transmission, set the
port SC data register (SCPDR) and port SC
control register (SCPCR), then clear the TE bit in
SCSCR to 0.
In steps 1 and 2, it is possible to ascertain the
number of data bytes that can be written from the
number of transmit data bytes in SCFTDR
indicated by the upper 8 bits of SCFDR.
Clear TE bit in SCSCR to 0
End of transmission
Figure 16.3 Sample Serial Transmission Flowchart
Rev. 2.00, 09/03, page 407 of 690