HD6417705 Datasheet, PDF (383/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

14.3.2 Timer Mode Registers (TMDR)
TMDR are 16-bit readable/writable registers that are used to set the operating mode for each
channel.
TMDR register settings should be made only when TCNT operation is stopped.
Initial
Bit
Bit Name Value
15 to 7 
0
6
BFWT
0
5
BFB
0
4
BFA
0
3

0
2
MD2
0
1
MD1
0
0
MD0
0
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be modified.
Buffer Write Timing
Specifies TGRA and TGRB update timing when TGRC and
TGRD are used as a compare match buffer. When TGRC
and TGRD are not used as a compare match buffer register,
this bit is ignored.
0: TGRA and TGRB are rewritten at compare match of each
register.
1: TGRA and TGRB are rewritten in counter clearing.
Buffer Operation B
Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer
operation.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation A
Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer
operation.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
Reserved
This bit is always read as 0 and cannot be modified.
Timer Operating Mode
Set the timer-operating mode.
000: Normal operation
001: Setting prohibited
010: PWM mode
011: Setting prohibited
1XX: Setting prohibited
Note: X: Don’t care
Rev. 2.00, 09/03, page 337 of 690