HD6417705 Datasheet, PDF (103/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 2.9 Shift Instructions
Instruction
ROTL
Rn
ROTR
Rn
ROTCL Rn
ROTCR Rn
SHAD
Rm, Rn
SHAL
SHAR
SHLD
Rn
Rn
Rm, Rn
SHLL
Rn
SHLR
Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Instruction Code Operation
0100nnnn00000100 T←Rn←MSB
0100nnnn00000101 LSB→Rn→T
0100nnnn00100100 T←Rn←T
0100nnnn00100101 T→Rn→T
0100nnnnmmmm1100 Rn ≥ 0: Rn << Rm → Rn
Rn < 0: Rn >> Rm → [MSB →
Rn]
0100nnnn00100000 T←Rn←0
0100nnnn00100001 MSB→Rn→T
0100nnnnmmmm1101 Rn ≥ 0: Rn << Rm → Rn
Rn < 0: Rn >> Rm → [0 → Rn]
0100nnnn00000000 T←Rn←0
0100nnnn00000001 0→Rn→T
0100nnnn00001000 Rn<<2 → Rn
0100nnnn00001001 Rn>>2 → Rn
0100nnnn00011000 Rn<<8 → Rn
0100nnnn00011001 Rn>>8 → Rn
0100nnnn00101000 Rn<<16 → Rn
0100nnnn00101001 Rn>>16 → Rn
Privileged
Mode
Cycles T Bit
–
1
MSB
–
1
LSB
–
1
MSB
–
1
LSB
–
1
–
–
1
MSB
–
1
LSB
–
1
–
–
1
MSB
–
1
LSB
–
1
–
–
1
–
–
1
–
–
1
–
–
1
–
–
1
–
Rev. 2.00, 09/03, page 57 of 690