HD6417705 Datasheet, PDF (141/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 4.2 LRU and Way Replacement (when Cache Locking Mechanism Is Disabled)
LRU (Bits 5 to 0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
2
1
0
4.2 Register Descriptions
The cache has the following registers. For details on register addresses and register states during
each process, refer to section 24, List of Registers.
• Cache control register 1 (CCR1)
• Cache control register 2 (CCR2)
• Cache control register 3 (CCR3)
Rev. 2.00, 09/03, page 95 of 690