HD6417705 Datasheet, PDF (172/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 6.1 shows a block diagram of the INTC.
NMI
IRQ5−IRQ0
PINT15−PINT0
DMAC
SCIF
ADC
USB
TMU
TPU
WDT
UDI
REF
RTC
Input/output
6
control
16
(Interrupt request)
Priority
identifier
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR
IRR
IPR
PINTER
Bus
interface
Legend:
DMAC : Direct memory access controller
SCIF : Serial communication interface (with FIFO)
ADC : A/D converter
USB : USB interface
TMU : Timer pulse unit
TPU : 16-bit timer pulse unit
INTC
WDT : Watchdog timer
UDI : User debugging interface
RTC : Realtime clock
REF : Refresh request in bus state controller
ICR : Interrupt control register
IPR : Interrupt priority level setting register
IRR : Interrupt request register
PINTER : PINT interrupt enable register
SR : Status register
Figure 6.1 Block Diagram of INTC
Rev. 2.00, 09/03, page 126 of 690