HD6417705 Datasheet, PDF (48/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 1.1 SH7705 Features
Item
Features
CPU
• Original Renesas SuperH architecture
• Compatible with SH-1, SH-2 and SH-3 at object code level
• 32-bit internal data bus
• General-registers
Sixteen 32-bit general registers (eight 32-bit shadow registers)
Five 32-bit control registers
Four 32-bit system registers
• RISC-type instruction set
Instruction length: 16-bit fixed length and improved code efficiency
Load/store architecture
Delayed branch instructions
Instruction set based on C language
• Instruction execution time: one instruction/cycle for basic instructions
Memory
management
unit (MMU)
• Logical address space: 4 Gbytes
• Five-stage pipeline
• 4 Gbytes of address space, 256 address space identifiers (ASID: 8 bits)
• Page unit sharing
• Supports multiple page sizes: 1 kbyte or 4 kbytes
• 128-entry, 4-way set associative TLB
• Supports software selection of replacement method and random-
replacement algorithms
• Contents of TLB are directly accessible by address mapping
Cache memory • 32-kbyte cache, mixture of instructions and data
• 512 entries, 4-way set associative, 16-byte block length
• Write-back, write-through, LRU replacement algorithm
•
Interrupt
•
controller (INTC) _•
1-stage write-back buffer
Seven external interrupt pins (NMI, IRQ5 to IRQ0)
On-chip peripheral interrupt: Priority level is independently selected for each
module
Rev. 2.00, 09/03, page 2 of 690