HD6417705 Datasheet, PDF (356/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 12.1 shows a block diagram of the TMU.
Pφ
TCLK
TUNI0
TUNI1
Prescaler
Clock
controller
Ch. 0
Counter
controller
Interrupt
controller
Ch. 1
Counter
controller
Interrupt
controller
Ch. 2
Counter
controller
TUNI2
TICPI2
Interrupt
controller
Legend:
TSTR: Timer start register
TCR_n: Timer control register
(n: 0, 1, 2)
Bus interface
TSTR
TCR_0
TCNT_0
TCOR_0
TCR_1
TCNT_1
TCOR_1
TCR_2
TCPR_2
TCNT_2
TCOR_2
TMU
TCNT_n: 32-bit timer counter
TCOR_n: 32-bit timer constant register
TCPR_2: 32-bit input capture register
Figure 12.1 TMU Block Diagram
Rev. 2.00, 09/03, page 310 of 690