HD6417705 Datasheet, PDF (226/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name
31 to 8 
7 to 0 
Initial
Value R/W
0
R
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Maximum Counter Value (eight bits)
7.4.8 Reset Wait Counter (RWTCNT)
RWTCNT is a 16-bit register. The lower seven bits of this register (bits 6 to 0) are valid as a
counter and the upper nine bits (bits 15 to 7) are reserved. This counter starts to count-up by
synchronizing the CKIO after a power-on reset is released. This counter stops when the value
reaches to H'007F. The access to an external bus has to wait when the counter is operating. This
counter is provided to minimize the time from releasing a reset for flash memory to the first
access. This counter cannot be read or written into.
7.5 Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte
data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low
level on power-on reset, the endian will become big endian and when MD5 pin is high level on
power-on reset, the endian will become little endian. Three data bus widths are available for
normal memory (byte, word, and longword). Word and longword are available for SDRAM. Data
bus width for address/data multiplex I/O (MPX) should be 16 bits. Data alignment is performed in
accordance with the data bus width of the device and endian. This also means that when longword
data is read from a byte-width device, the read operation must be done four times. In this LSI, data
alignment and conversion of data length is performed automatically between the respective
interfaces.
Tables 7.4 to 7.9 show the relationship between endian, device data width, and access unit.
Rev. 2.00, 09/03, page 180 of 690