HD6417705 Datasheet, PDF (277/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
A12/A11^*1
Tp
Tpw
Trr
Trc
PALL
REF
Trc
Trr
Trc
REF
Trc Tmw Tnop
MRS
CSn
RASU/L
CASU/L
RD/WR
DQMxx^*2
D31 to D0
BS
DACKn^*3
Hi-Z
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. xx is UU, UL, LU, or LL.
3. The waveform for DACKn is when active low is specified.
Figure 7.29 Synchronous DRAM Mode Write Timing (Based on JEDEC)
7.9 Burst ROM Interface
The burst ROM interface is provided to access ROM that has the page mode function, such as
flash memory, in high speed. Basically the access to the ROM is performed in the same way as for
normal space. When the first cycle is terminated, however, negation of the RD signal is not
executed. The accesses after the 2nd access are performed by exchanging only the address. In the
accesses after the 2nd access, the address is changed at the falling edge of CKIO.
The number of wait cycles specified by the W[3:0] bits in CSnWCR are inserted for the first
access cycle. The number of wait cycles specified by the BW[1:0] bits in CSnWCR are inserted
for the second and subsequent access cycles.
In the access to the burst ROM, the BS signal is asserted only to the first access cycle. An external
wait input is valid only to the first access cycle. In the single access or write access that do not
perform the burst operation in the burst ROM interface, access timing is same as a normal space.
Table 7.18 lists a relationship between bus width, access size, and the number of bursts. Figure
7.30 shows a timing chart.
Rev. 2.00, 09/03, page 231 of 690