HD6417705 Datasheet, PDF (486/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.3 Register Descriptions
The USB has following registers. For the information on the addresses of these registers and the
state of the register in each processing condition, see section 24, List of Registers.
• Interrupt flag register 0 (IFR0)
• Interrupt flag register 1 (IFR1)
• Interrupt select register 0 (ISR0)
• Interrupt select register 1 (ISR1)
• Interrupt enable register 0 (IER0)
• Interrupt enable register 1 (IER1)
• EP0i data register (EPDR0i)
• EP0o data register (EPDR0o)
• EP0s data register (EPDR0s)
• EP1 data register (EPDR1)
• EP2 data register (EPDR2)
• EP3 data register (EPDR3)
• EP0o receive data size register (EPSZ0o)
• EP1 receive data size register (EPSZ1)
• Trigger register (TRG)
• Data status register (DASTS)
• FIFO clear register (FCLR)
• DMA transfer setting register (DMAR)
• Endpoint stall register (EPSTL)
• Transceiver control register (XVERCR)
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