HD6417705 Datasheet, PDF (13/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Item
7.13 Others
Reset
Page
237
8.3.4 DMA Channel
244
Control Registers (CHCR)
245
8.4.3 Channel Priority
258
Round-Robin Mode
8.4.4 DMA Transfer Types 262
Address Modes
Figure 8.6 Example of
DMA Transfer Timing in
Dual Mode (Source:
Ordinary Memory,
Destination: Ordinary
Memory)
Revisions (See Manual for Details)
In standby, sleep, and manual reset, control registers of the
bus state controller are not initialized. At manual reset, the
current bus cycle being executed is completed and then the
access wait state is entered. Since the RTCNT continues
counting up during manual reset signal assertion, a refresh
request occurs to initiate the refresh cycle.
Note that arbitration requests using BREQ are not accepted
during manual reset signal assertion.
Bits 15, 14 description amended
00: Fixed destination address
(setting prohibited in 16-byte transfer)
Bits 13, 12 description amended
00: Fixed source address
(setting prohibited in 16-byte transfer)
⋅⋅⋅⋅⋅ The priority of round-robin mode is CH0 > CH1 > CH2 >
CH3 immediately after a reset.
When the round-robin mode is specified, cycle-steal mode
and burst mode should not be mixed among the bus modes
for multiple channels.
Figure amended
CKIO
A25 to A0
Transfer source
address
Transfer destination
address
CSn
D31 to D0
Bus Mode and channel
Priority Order
8.5 Precautions
266
RD
WEn
DACKn
(Active-Low)
Data read cycle
(1st cycle)
Description largely revised
270 Newly added
Data write cycle
(2nd cycle)
Rev. 2.00, 09/03, page xiii of xlvi