HD6417705 Datasheet, PDF (40/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: READ Command, Same Row Address,
CAS Latency = 2, TRCD = 1 Cycle) ................................................................. 655
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: PRE + ACTV + READ Commands,
Different Row Address, CAS Latency = 2, TRCD = 1 Cycle)............................ 656
Figure 25.33 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: ACTV + WRITE Commands, TRCD = 1 Cycle,
TRWL = 1 Cycle)............................................................................................. 657
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: WRITE Command, Same Row Address,
TRCD = 1 Cycle, TRWL = 1 Cycle) ................................................................. 658
Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: PRE + ACTV + WRITE Commands,
Different Row Address, TRCD = 1 Cycle, TRWL = 1 Cycle)............................ 659
Figure 25.36 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle) ............................. 660
Figure 25.37 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle) .............................. 661
Figure 25.38 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle).................. 662
Figure 25.39 Access Timing in Low-Frequency Mode (Auto Precharge) ................................ 664
Figure 25.40 Synchronous DRAM Auto-Refresh Timing
(TRP = 2 Cycle, Low-Frequency Mode) ............................................................ 665
Figure 25.41 Synchronous DRAM Self-Refresh Timing
(TRP = 2 Cycle, Low-Frequency Mode) ............................................................ 666
Figure 25.42 Synchronous DRAM Mode Register Write Timing
(TRP = 2 Cycle, Low-Frequency Mode) ............................................................ 667
Figure 25.43 DREQ Input Timing ......................................................................................... 668
Figure 25.44 DACK, TEND Output Timing .......................................................................... 668
Figure 25.45 TCLK Input Timing.......................................................................................... 669
Figure 25.46 TCLK Clock Input Timing................................................................................ 669
Figure 25.47 Oscillation Settling Time when RTC Crystal Oscillator Is Turned On ................ 670
Figure 25.48 TPU Output Timing .......................................................................................... 670
Figure 25.49 SCK Input Clock Timing .................................................................................. 671
Figure 25.50 SCIF Input/Output Timing in Clock Synchronous Mode.................................... 672
Figure 25.51 USB Clock Timing ........................................................................................... 672
Figure 25.52 Oscillation Settling Time when USB Crystal Oscillator Is Turned On ................ 673
Figure 25.53 I/O Port Timing ................................................................................................ 674
TRST ^{Figure 25.54 TCK Input Timing ............................................................................................ 675}
Figure 25.55
Input Timing (Reset Hold) ...................................................................... 676
ASEMD0 ^{Figure 25.56 UDI Data Transfer Timing ................................................................................ 676}
Figure 25.57
Input Timing..................................................................................... 676
Figure 25.58 Output Load Circuit .......................................................................................... 677
Rev. 2.00, 09/03, page xl of xlvi