HD6417705 Datasheet, PDF (208/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

1. Normal Space, Byte-Selection SRAM, Address/Data Multiplex I/O (MPX)
CS0WCR, CS6AWCR, CS6BWCR
Initial
Bit Bit Name Value R/W
31 to 13 
0
R
12
SW1 0
R/W
11
SW0 0
R/W
10
WR3 1
R/W
9
WR2 0
R/W
8
WR1 1
R/W
7
WR0 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to RD,
WEn Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Number of Access Wait Cycles
Specify the number of cycles that are necessary for read/write
access.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
Rev. 2.00, 09/03, page 162 of 690