HD6417705 Datasheet, PDF (199/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Area
Memory to be
Connected
Physical Address
Access
Capacity Size
Area 1
Internal I/O register^*7
H'04000000
H'04000000
+H'20000000×n
to H'07FFFFFF
to H'07FFFFFF
+H'20000000×n
(n:1 to 6)
Area 2
Normal memory^*1,
Synchronous DRAM
H'08000000
H'08000000
+H'20000000×n
to H'0BFFFFFF
to H'0BFFFFFF
+H'20000000×n
64 Mbytes
Shadow
8, 16, 32^{*3, *5}
(n:1 to 6)
Area 3
Normal memory^*1,
Synchronous DRAM
H'0C000000
H'0C000000
+H'20000000×n
to H'0FFFFFFF
to H'0FFFFFFF
+H'20000000×n
64 Mbytes
Shadow
8, 16, 32^{*3, *5}
(n: 1 to 6)
Area 4
Normal memory^*1,
Burst ROM,
Byte-selection SRAM
H'10000000
H'10000000
+H'20000000×n
to H'13FFFFFF
to H'13FFFFFF
+H'20000000×n
64 Mbytes
Shadow
8, 16, 32^*3
(n: 1 to 6)
Area 5A _{Normal memory}*¹
H'14000000
to H'15FFFFFF 32 Mbytes _{8, 16, 32}*³
H'14000000
to H'15FFFFFF Shadow (n: 1 to 6)
+H'20000000×n +H'20000000×n
Area 5B
Normal memory^*1,
Address/data multiplex
I/O (MPX), Byte-
selection SRAM
H'16000000
H'16000000
+H'20000000×n
to H'17FFFFFF
to H'17FFFFFF
+H'20000000×n
32 Mbytes
Shadow
8, 16^{*3, *4}
(n: 1 to 6)
Area 6A _{Normal memory}*¹
H'18000000
to H'19FFFFFF 32 Mbytes _{8, 16}*³
H'18000000
to H'19FFFFFF Shadow (n: 1 to 6)
+H'20000000×n +H'20000000×n
Area 6B _{Normal memory}*¹
H'1A000000
to H'1BFFFFFF 32 Mbytes _{8, 16}*³
H'1A000000
to H'1BFFFFFF Shadow (n: 1 to 6)
+H'20000000×n +H'20000000×n
Area 7^{*6 Reserved area}
H'1C000000
to H'1FFFFFFF
+H'20000000×n +H'20000000×n
(n: 0 to 7)
Notes: 1. Memory that has an interface such as SRAM or ROM.
2. Memory bus width is specified by an external pin.
3. Memory bus width is specified by a register.
4. With the address/data multiplex I/O (MPX) interface, the bus width must be 16 bits.
5. With the SDRAM, the bus width must be 16 bits or 32 bits.
6. Do not access the reserved area. If the reserved area is accessed, the operation cannot
be guaranteed.
7. When the addresses of the on-chip module control registers (internal I/O registers) in
area 1 are not translated by the MMU, set the top three bits of the logical addresses to
101 to allocate in the P2 space.
Rev. 2.00, 09/03, page 153 of 690