HD6417705 Datasheet, PDF (312/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 8.9
shows the relationship between request modes and bus modes by DMA transfer category.
Table 8.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address
Mode Transfer Category
Request Bus Transfer Usable
Mode Mode Size (bits) Channels
Dual
External device with DACK and external
memory
External B/C 8/16/32/128 0, 1
External device with DACK and memory-
mapped external device
External B/C 8/16/32/128 0, 1
External memory and external memory
All^*1
B/C 8/16/32/128 _{0 to 3}*⁵
External memory and memory-mapped
external device
All^*1
B/C 8/16/32/128 _{0 to 3}*⁵
Memory-mapped external device and
memory-mapped external device
All^*1
B/C 8/16/32/128 _{0 to 3}*⁵
External memory and on-chip peripheral
All^*2
module
B/C^*3 8/16/32/128^*4 0 to 3^*5
Memory-mapped external device and
on-chip peripheral module
All^*2
B/C^*3 8/16/32/128^*4 0 to 3^*5
On-chip peripheral module and on-chip
peripheral module
All^*2
B/C^*3 8/16/32/128^*4 0 to 3^*5
Single External device with DACK and external External B/C 8/16/32
0, 1
memory
External device with DACK and memory- External B/C 8/16/32
0, 1
mapped external device
B: Burst, C: Cycle steal
Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all
available. In the case of on-chip peripheral module requests, however, the CMT is only
available.
2. External requests, auto requests, and on-chip peripheral module requests are all
available. However, with the exception of the CMT, the module must be designated as
the transfer request source or the transfer destination.
3. Only cycle steal except for the CMT as the transfer source.
4. Access size permitted for the on-chip peripheral module register functioning as the
transfer source or transfer destination.
5. If the transfer request is an external request, channels 0 and 1 are only available.
Bus Mode and Channel Priority Order: If, when the priority is set to fixed mode (CH0 > CH1)
and channel 1 is transferring in burst mode, a transfer request to channel 0, which has higher
priority, is generated, the transfer on channel 0 will begin immediately.
At this time, if channel 0 is set to burst mode, the transfer on channel 1 will resume when the
channel 0 transfer has completely finished.
Rev. 2.00, 09/03, page 266 of 690