HD6417705 Datasheet, PDF (267/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
Tw
Td1
Td2
Td3
Td4
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
Tde
A25 to A0
A12/A11^*1
CSn
RASU/L
CASU/L
RD/WR
DQMxx^*2
D31 to D0
BS
DACKn^*3
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. xx is UU, UL, LU, or LL.
3. The waveform for DACKn is when active low is specified.
Figure 7.22 Burst Read Timing (Bank Active, Different Row Addresses)
Rev. 2.00, 09/03, page 221 of 690