HD6417705 Datasheet, PDF (346/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

11.5 Software Standby Mode
11.5.1 Transition to Software Standby Mode
The LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit is 1 in STBCR. In software standby mode, not only the
CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin
also halts.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. For more details on the states of on-chip peripheral
modules registers in software standby mode, refer to section 24.3, Register States in Each
Operating Mode.
The procedure for moving to software standby mode is as follows:
1. Clear the TME bit in the WDT’s timer control register (WTCSR) to 0 to stop the WDT.
2. Clear the WDT’s timer counter (WTCNT) to 0 and set the CKS2 to CKS0 bits in WTCSR to
appropriate values to secure the specified oscillation settling time.
3. After the STBY bit in STBCR is set to 1, a SLEEP instruction is executed.
4. Software standby mode is entered and the clocks within the LSI are halted. The STATUS1 pin
output goes low and the STATUS0 pin output goes high.
11.5.2 Canceling Software Standby Mode
Software standby mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, or RTC) or a reset.
Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects
an NMI, IRQ*¹, IRL*¹, PINT*¹, or RTC*¹ interrupt, the clock will be supplied to the entire chip
and software standby mode canceled after the time set in the WDT’s timer control/status register
has elapsed. The STATUS1 and STATUS0 pins both go low. Interrupt exception handling then
begins and a code indicating the interrupt source is set in INTEVT and INTEVT2. After branching
to the interrupt handling routine occurs, clear the STBY bit in STBCR. WTCNT stops
automatically. If the STBY bit is not cleared, WTCNT continues operation and transits to software
standby mode*² when it reaches H'80. This function prevents data from being broken in case of a
voltage rise when the power supply is unstable. At this time, a manual reset is not accepted until
the STBY bit is cleared to 0.
Interrupts are accepted in software standby mode even when the BL bit in SR is 1. If necessary,
save SPC and SSR to the stack before executing the SLEEP instruction.
Immediately after an interrupt is detected, the phase of the clock output of the CKIO pin may be
unstable, until software standby mode is cancelled.
Rev. 2.00, 09/03, page 300 of 690