HD6417705 Datasheet, PDF (335/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit
Name Value R/W
Description
2
CKS2 0
R/W
Clock Select 2 to 0
1
CKS1 0
R/W
These bits select the clock to be used for the WTCNT
0
CKS0 0
R/W
count from the eight types obtainable by dividing the
peripheral clock. The overflow period that is shown
inside the parenthesis in the table is the value when
the peripheral clock (Pφ) is 15 MHz.
000
Pφ
(17 µs)
001
Pφ/4
(68 µs)
010
Pφ/16
(273 µs)
011
Pφ/32
(546 µs)
100
Pφ/64
(1.09 ms)
101
Pφ/256
(4.36 ms)
110
Pφ/1024
(17.48 ms)
111
Pφ/4096
(69.91 ms)
Note:
If bits CKS2 to CKS0 are modified when the
WDT is running, the up-count may not be
performed correctly. Ensure that these bits are
modified only when the WDT is not running.
Note:
If manual reset is selected using the RSTS bit, a frequency division ratio of 1/16, 1/32, 1/64,
1/256, 1/1,024, or 1/4,096 is selected using bits CKS2 to CKS0, and a watchdog timer
counter overflow occurs, resulting in a manual reset, the LSI will generate two manual
resets in succession. This will not affect its operation but will cause change in the state of
the STATUS pin.
10.2.3 Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
• These registers must be written by a word transfer instruction. They cannot be written by a
byte or longword transfer instruction.
When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data,
as shown in figure 10.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the
lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or
WTCSR.
Rev. 2.00, 09/03, page 289 of 690