HD6417705 Datasheet, PDF (258/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8.3 Burst Read
A burst read occurs in the following cases in this LSI.
• 16-byte transfer in cache miss.
• 16-byte transfer in DMAC (access to non-cacheable region)
• Access size in reading is larger than data bus width.
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that
is connected to a 32-bit data bus.
Table 7.16 shows the relationship between the access size and the number of bursts.
Table 7.16 Relationship between Access Size and Number of Bursts
Bus Width
16 bits
32 bits
Access Size
8 bits
16 bits
32 bits
16 bits
8 bits
16 bits
32 bits
16 bits
Number of Bursts
1
1
2
8
1
1
1
4
Rev. 2.00, 09/03, page 212 of 690