HD6417705 Datasheet, PDF (200/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

H'00000000
H'20000000
P0
H'40000000
H'60000000
H'80000000
P1
H'A0000000
P2
H'C0000000
P3
H'E0000000
P4
Area 0 (CS0)
Internal I/O
Area 2 (CS2)
Area 3 (CS3)
Area 4 (CS4)
Area 5A (CS5A)
Area 5B (CS5B)
Area 6A (CS6A)
Area 6B (CS6B)
Reserved area
H'00000000
H'04000000
H'08000000
H'0C000000
H'10000000
H'14000000
H'16000000
H'18000000
H'1A000000
H'1BFFFFFF
Physical address space
Logical address space
Note: For logical address spaces P0 and P3, when the memory management unit (MMU) is on, it can
optionally generate a physical address for the logical address. This figure can be applied when
MMU is off and when the MMU is on and each physical address for the logical address is equal
except for higher three bits. When translating a logical address to a physical address, refer to
table 7.2.
Figure 7.2 Address Space
7.3.2 Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to
select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The correspondence
between the external pins (MD3, MD4) and memory size is listed in the table below.
Table 7.3 Correspondence between External Pins (MD3 and MD4) and Memory Size
MD4
0
1
MD3
0
1
0
1
Memory Size
Setting prohibited
8 bits
16 bits
32 bits
For areas other than area 0, byte, word, and longword may be chosen for the bus width using
CSnBCR that can be set in each area. The bus width that can be set differs according to a
connected interface. For more details, see the CSn Bus Control Register.
Rev. 2.00, 09/03, page 154 of 690