HD6417705 Datasheet, PDF (707/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
A12/A11^*1
Tp
t_AD1
t_AD1
Tpw
Trr
Trc
t_AD1
t_AD1
CSn
RD/WR
RASU/L
CASU/L
t_CSD1
t_CSD1
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
Trc
Trc
Trc
Trc
t_RWD1
DQMxx
D31 to D0
(Hi-Z)
BS
CKE
t_CKED1
t_CKED1
DACKn^*2
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.37 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle)
Rev. 2.00, 09/03, page 661 of 690