HD6417705 Datasheet, PDF (313/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

On the other hand, if channel 0 is operating in cycle-steal mode, channel 1 will begin operating
again after channel 0 completes the transfer of one transfer unit, and without the internal bus being
released. Transfer will then alternate between the two channels in the order channel 0, channel 1,
channel 0, channel 1, and so on. In other words, the CPU cycles following cycle-steal mode
transfer are replaced by bust mode transfer. Figure 8.12 shows an example of this. If multiple
channels are competing to execute burst mode transfers, the channel with the highest priority
performs the burst mode transfer first.
When DMA transfers are performed using multiple channels, the bus is not released to another bus
master until all of the competing burst mode transfers have completed.
CPU
DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH1
CH0
CH1
CH0
CPU
CPU
DMAC CH1
burst mode
Priority: CH0 > CH1
CH0: Cycle-steal mode
CH1: Burst mode
Cycle-steal mode between
DMAC CH0 and CH1
DMAC CH1
burst mode
CPU
Figure 8.12 Bus State when Multiple Channels are Operating
Cycle-steal mode channels and burst mode channels should not be mixed in round-robin mode.
Doing so runs the risk that priority changes may not be made properly, although the individual
channel transfer operations will be performed correctly.
8.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 7, Bus State Controller (BSC).
DREQ Pin Sampling Timing:
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
DMAC
CPU
1st acceptance
Non sensitive period
2nd acceptance
Acceptance start
Figure 8.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Rev. 2.00, 09/03, page 267 of 690