HD6417705 Datasheet, PDF (508/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.4.5 EP2 Bulk-In Transfer (Dual FIFOs)
USB function
IN token reception
Application
Valid data
in EP2 FIFO?
Yes
No
NACK
Interrupt request
Data transmission to host
ACK
Clear EP2 transfer
request flag
(IFR0.EP2 TR = 0)
Enable EP2 FIFO
empty interrupt
(IER0.EP2 EMPTY = 1)
Space
Yes
in EP2 FIFO?
No
Clear EP2 empty status
(IFR0.EP2 EMPTY = 0)
Set EP2
empty status
(IFR0.EP2
EMPTY = 1)
Interrupt
request
IER0.EP2 EMPTY
interrupt
Write one packet of data
to EP2 data register
(EPDR2)
Write 1 to EP2 packet
enable bit
(TRG.EP2 PKTE = 1)
Figure 18.11 EP2 Bulk-In Transfer Operation
EP2 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being
aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For
example, even if both FIFOs are empty, it is not possible to perform EP2PKTE at one time after
consecutively writing 128 bytes of data. EP2PKTE must be performed for each 64-byte write.
When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first
IN token, an EP2TR bit interrupt in IFR0 is requested. With this interrupt, 1 is written to the
EP2EMPTY bit in IER0, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs
are empty, and so an EP2 FIFO empty interrupt is generated immediately.
The data to be transmitted is written to the data register using this interrupt. After the first transmit
data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to
the other FIFO immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one
FIFO is empty, the EP2EMPTY bit in IFR0 is set to 1. When ACK is returned from the host after
Rev. 2.00, 09/03, page 462 of 690