HD6417705 Datasheet, PDF (461/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

When using a modem function and the receive FIFO (SCFRDR) is at least the number of the RTS
output trigger, the RTS signal goes high.
Figure 16.11 shows an example of operation for the RTS control.
Transmit data
TxD
Start
bit
0 D0 D1
Parity Stop
bit bit
D6 D7 0/1
RTS
RTS goes high when receive data is RTS goes low when receive data is
at least number of RTS output trigger less than number of RTS output trigger
Figure 16.11 RTS Control Operation
16.4.4 Clock Synchronous Mode
64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed.
The operating clock source is selected using the serial mode register (SCSMR). The SCIF clock
source is determined by the CKE1 and CKE0 bits in the serial control register (SCSCR).
• Transmit/receive format: Fixed 8-bit data
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Internal clock or external clock used as the SCIF clock source
When the internal clock is selected:
The SCIF operates on the baud rate generator clock and outputs a serial clock from SCK pin.
When the external clock is selected:
The SCIF operates on the external clock input through the SCK pin.
Rev. 2.00, 09/03, page 415 of 690