HD6417705 Datasheet, PDF (581/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

A/D conversion time (t_CONV)
A/D conversion start delay time (t_D) Analog input sampling time (t_SPL)
Write cycle A/D
synchronization time
Pφ
Address
Internal
write signal
Analog input
sampling signal
Write timing of ADST
A/D converter
Idle time
Sample and hold A/D conversion executed
ADF
A/D conversion ended
Figure 21.2 A/D Conversion Timing
Table 21.3 A/D Conversion Time (Single Mode)
CKS1 = 1,
CKS0 = 0
Symbol Min Typ Max
A/D conversion start tD
delay
18 — 21
Input sampling time tSPL
— 129 —
A/D conversion time tCONV
535 — 545
Note: Values in the table are numbers of states for Pφ.
CKS1 = 0,
CKS0 = 1
Min Typ Max
10 — 13
— 65 —
275 — 285
CKS1 = 0,
CKS0 = 0
Min Typ Max
6
—9
— 33 —
141 — 151
Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode)
CKS1
0
0
1
1
CKS0
0
1
0
1
Conversion Time (cycles)
128 (fixed)
256 (fixed)
512 (fixed)
Unused
Rev. 2.00, 09/03, page 535 of 690