HD6417705 Datasheet, PDF (286/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 8.1 shows the block diagram of the DMAC.
On-chip
peripheral module
DMAC module
Transfer count
control
Register
control
Start-up
control
SAR_n
DAR_n
DMATCR_n
CHCR_n
DREQ0, DREQ1
SCIF0, SCIF2
CMT, USB
A/D converter
DEIn
DACK0, DACK1
TEND0
Request
priority
control
DMAOR
DMARS0−1
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge-
ment)
Bus
interface
Bus state
controller
[Legend]
DMAOR: DMA operation register
SARn:
DMA source address register
DARn:
DMA destination address register
DMATCRn: DMA transfer count register
CHCRn: DMA channel control register
DMARS0/1: DMA extension resource selector
DEIn:
DMA transfer-end interrupt request to the CPU
n : 0, 1, 2, 3
Figure 8.1 Block Diagram of DMAC
Rev. 2.00, 09/03, page 240 of 690