HD6417705 Datasheet, PDF (390/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

• Free-running count operation and periodic count operation
Immediately after a reset, the TPU’s TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-
count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000),
the TCFV bit in TSR is set to 1. After overflow, TCNT starts counting up again from H'0000.
Figure 14.3 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
CST bit
Time
TCFV
Figure 14.3 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The TGR register for setting the period is designated
as an output compare register, and counter clearing by compare match is selected by means of bits
CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as
a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches
the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
After a compare match, TCNT starts counting up again from H'0000.
Figure 14.4 illustrates periodic counter operation.
TCNT value
TGRA
Counter cleared by TGRA
compare match
H'0000
CST bit
TGFA
Time
Flag cleared by software
Figure 14.4 Periodic Counter Operation
Rev. 2.00, 09/03, page 344 of 690