HD6417705 Datasheet, PDF (209/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Initial
Bit Bit Name Value R/W
6
WM
0
R/W
5 to 2 
0
R
1
HW1 0
R/W
0
HW0 0
R/W
Description
External Wait Mask Specification
Specifies whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
Delay Cycles from RD, WEn negation to Address, CSn
negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 2.00, 09/03, page 163 of 690