HD6417705 Datasheet, PDF (239/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 7.9. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T₁ or Tw
cycle to the T₂ cycle.
CKIO
A25 to A0
CSn
RD/WR
Read
RD
Data
Write
WEn
Data
WAIT
BS
DACKn*
Wait states inserted
by WAIT signal
T₁
Tw
Tw
Twx
T₂
Note: * The waveform for DACKn is when active low is specified.
WAIT ^{Figure 7.9 Wait State Timing for Normal Space Access}
(Wait State Insertion by
Signal)
Rev. 2.00, 09/03, page 193 of 690