HD6417705 Datasheet, PDF (91/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

2.5.3 CPU Instruction Formats
Table 2.4 shows the instruction formats, and the meaning of the source and destination operands,
for instructions executed by the CPU core. The meaning of the operands depends on the
instruction code. The following symbols are used in the table.
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii:
Immediate data
dddd: Displacement
Table 2.4 CPU Instruction Formats
Instruction Format
0 type
15
0
xxxx xxxx xxxx xxxx
n type
15
0
xxxx nnnn xxxx xxxx
m type
15
0
xxxx mmmm xxxx xxxx
Source
Operand
—
Destination
Operand
—
Sample Instruction
NOP
—
nnnn: register
MOVT Rn
direct
Control register or nnnn: register
system register direct
STS MACH,Rn
Control register or nnnn: pre-
STC.L SR,@-Rn
system register decrement register
indirect
mmmm: register Control register or LDC Rm,SR
direct
system register
mmmm: post-
Control register or LDC.L @Rm+,SR
increment register system register
indirect
mmmm: register —
indirect
JMP @Rm
PC-relative using —
Rm
BRAF Rm
Rev. 2.00, 09/03, page 45 of 690