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HD6417705 Datasheet, PDF (592/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series
22.2.5 Break Address Mask Register B (BAMRB)
BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address
specified by BARB.
Bit
Initial
Bit
Name
Value R/W
31 to 0 BAMB31 0
R/W
to
BAMB0
Description
Break Address Mask B
Specifies bits masked in the break address of channel B
specified by BARB (BAB31 to BAB0).
0: Break address BABn of channel B is included in the
break condition
1: Break address BABn of channel B is masked and is
not included in the break condition
Note: n = 31 to 0
22.2.6 Break Data Register B (BDRB)
BDRB is a 32-bit readable/writable register.
Bit
Initial
Bit
Name
Value R/W Description
31 to 0 BDB31 to 0
BDB0
R/W Break Data Bit B
Stores data which specifies a break condition in channel
B.
BDRB specifies the break data on LDB or IDB.
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDRB as the break data.
Rev. 2.00, 09/03, page 546 of 690