HD6417705 Datasheet, PDF (699/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
A12/A11^*1
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Trwl
t_AD1
t_AD1
t_AD1
Row address
t_AD1
t_AD1
Column
address
t_AD1
(1-4)
t_AD1
t_AD1
Write command
t_AD1
t_AD1
Write A
command
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
BS
t_CSD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
t_CSD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
CKE
DACKn^*2
t_DACD
(High)
t_DACD
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
(Auto Precharge, TRCD = 2 Cycle, TRWL = 2 Cycle)
Rev. 2.00, 09/03, page 653 of 690