HD6417705 Datasheet, PDF (190/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 6.6 Interrupt Level and INTEVT Code
Interrupt level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
INTEVT Code
H'200
H'220
H'240
H'260
H'280
H'2A0
H'2C0
H'2E0
H'300
H'320
H'340
H'360
H'380
H'3A0
H'3C0
6.5 Operation
6.5.1 Interrupt Sequence
The sequence of interrupt operations is described below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
following the priority levels set in the interrupt priority level setting registers A to H (IPRA to
IPRH). Lower priority interrupts are held pending. If two of these interrupts have the same
priority level or if multiple interrupts occur within a single module, the interrupt with the
highest priority is selected, according to tables 6.4 and 6.5.
3. The priority level of the interrupt selected by the interrupt controller is compared with the
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in
synchronization with the peripheral clock (Pφ). The CPU receives an interrupt at a break in
instructions.
Rev. 2.00, 09/03, page 144 of 690