HD6417705 Datasheet, PDF (210/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CS2WCR, CS3WCR
Bit
Bit Name
31 to 11 
Initial
Value R/W
0
R
10
WR3 1
R/W
9
WR2 0
R/W
8
WR1 1
R/W
7
WR0 0
R/W
6
WM
0
R/W
5 to 0 
0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Access Wait Cycles
Specify the number of cycles that are necessary for read/write
access.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 164 of 690